Showing posts with label level. Show all posts
Showing posts with label level. Show all posts

Thursday, November 20, 2014

Audio VU Level Meter Circuit with LM324

AudioAudio VU Level Meter Circuit with LM324

The 1K resistors in the circuit are capital so that the LEDs about-face on at altered audio levels. There is no acumen why you cant change these resistors, although annihilation aloft 5K may account some of the LEDs to never about-face on. This ambit is calmly abundant with added op-amps, and is not bound to use with the LM324. Pretty abundant any op-amp will assignment as continued as you attending up the pinouts and accomplish abiding aggregate is appropriately connected.

The 33K resistor on the schematic is to accumulate the arresting ascribe to the ambit at a low level. It is absurd you will acquisition a 33K resistor, so the abutting you can get should do. The amount of this resistor may charge to be changed, so it is best you breadboard this ambit afore absolutely amalgam it on PCB. The ambit in its accepted anatomy will acquire band akin inputs from sources such as the aux out on a Hi-Fi, all admitting could be calmly adapted to acquire apostle inputs.

The audio + is affiliated to the capital absolute rail, while the audio - is acclimated for arresting input. The 50k pot can be acclimated to alter the acuteness of the circuit.

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Thursday, November 6, 2014

Numeric Water Level Indicator

Most water-level indicators for water tanks are based upon the number of LEDs that glow to indicate the corresponding level of water in the container. Here we present a digital version of the water-level indicator. It uses a 7-segment display to show the water level in numeric form from0 to 9. The circuit works off 5V regulated power supply. It is built around priority encoder IC 74HC147 (IC1), BCD-to-7-segment decoder IC CD4511 (IC2), 7-segment display LTS543 (DIS1) and a few discrete components. Due to high input impedance, IC1 senses water in the container from its nine input terminals. The inputs are connected to +5V via 560-kilo-ohm resistors.

The ground terminal of the sensor must be kept at the bottom of the container (tank). IC 74HC147 has nine active-low inputs and converts the active input into active-low BCD output. The input L-9 has the highest priority. The outputs of IC1 (A, B, C and D) are fed to IC2 via transistors T1 through T4. This logic inverter is used to convert the active-low output of IC1 into active-high for IC2. The BCD code received by IC2 is shown on 7-segment display LTS543. Resistors R18 through R24 limit the current through the display.image
When the tank is empty, all the inputs of IC1 remain high. As a result, its output also remains high, making all the inputs of IC2 low. Display LTS543 at this stage shows 0, which means the tank is empty. Similarly, when the water level reaches L-1 position, the display shows 1, and when the water level reaches L-8 position, the display shows 8. Finally, when the tank is full, all the inputs of IC1 become low and its output goes low to make all the inputs of IC2 high. Display LTS543 now shows 9, which means the tank is full. Assemble the circuit on a general-purpose PCB and enclose in a box. Mount 7-segment LTS543 on the front panel of the box. For sensors L-1 though L-9 and ground, use corrosion-free conductive-metal (stainless-steel) strips.
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Wednesday, September 10, 2014

Scarce Level Power Fet Driver Method Wiring diagram Schematic

This is the Scarce Level Power Fet Driver Method Circuit Diagram. This schema operates from a 16- to 50-V supply. Adding the buffer schema (within the dashed lines) offers 100-ns switching times. Otherwise, the schema switches in 1 /xs. Ql and R1 form a switched current source of about 12 mA. 

The current flows through R2, which supplies 12 V to the FET. The schema works well over a wide range of supply voltages. Furthermore, it switches smoothly in the presence of large ripple and noise on the supply. 

 Scarce Level Power Fet Driver Method Circuit Diagram


Scarce


The switching time (about 1 /as) can be reduced considerably by lowering the values of Ri and R2 at the expense of higher power dissipation in the resistors and Ql. Alternatively, a buffer schema can be added to produce switching times of 100 ns without generating significant power dissipation.
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